Monthly Archives: May 2012

It’s an All Programmable Planet

Max Maxfield, Editor in Chief of the new UBM/Xilinx site All Programmable Planet:

“We are interested in all the things that have to do with programmable “stuff.” … All this explains why any system architect or hardware design engineer looking at creating any form of electronic system or product now includes programmable devices in all their forms in the deliberations.”

Notice also the same marketing slogan at “All Programmable technologies and devices”. No longer mere programmable logic.

I speculate that this is a new community site for Xilinx users which, with the launch of Zync EPP and Vivado high level tools and the roll-out of 7 Series devices, will drive new marketing messaging that repositions Xilinx products: as mainstream system design platforms and tools, applicable to any problem. No longer are FPGAs just for glue, low volume ASIC prototyping, routers, base stations, or custom accelerators. No longer are they relegated to the data plane, subordinate to some other embedded processor SoC. Rather with arrival of Zync, start to think of their product line as fast time-to-market platforms and tools for developing and shipping complete integrated systems, including volume consumer electronics. Expect to see a much greater emphasis on high level software assets — preported OSs (Linux, Android, …), applications frameworks (TV, automotive, medical), and targeted design platforms and kits, and more product love for embedded systems designers and software developers.

Xilinx has picked an apt slogan that nicely captures the value proposition of its programmable logic All Programmable platforms.

UPDATE: See also the Xilinx Company Overview page which makes this quite explicit. Xilinx technologies have evolved from “Programmable Logic Devices”; now “All Programmable Devices Enables Programmable Systems ‘Integration'”.

The Autumn of Moore’s Law: Scaling Up Computer Performance, 2011-2020

In 2010 and 2011 I gave this survey talk on prospects for continued exponential scaling of computer performance for the Singularity University Graduate Studies Program, in Mountain View, CA.

It is in three parts: prospects for continued transistor scaling; the transition to parallel computer architecture; and the challenges of writing mainstream software for parallel computers.

Hello again, world

It has been about nine years since my last blog post at FPGA CPU News. How’s that for taking a break?

Back then I returned to Microsoft as a performance architect on the .NET Common Language Runtime. (Example.) Around 2004 it became clear that clock frequency scaling was at its asymptotic end and future performance scaling would increasingly come from parallel computing. I spent the next five years working to get Microsoft’s client software stack, and in particular its developer platform and tools ready for mainstream multi-core, manycore, and heterogeneous platforms. My mission was “to provide loveable parallel programming models, tools, and infrastructure that enable any developer to write robust software that scales up on new hardware”. I led a product incubation on transactional memory and 2007-09 I helped define and build Microsoft’s Parallel Computing Platform strategy, team, and software, some of which shipped in Visual Studio 2010.

I have missed blogging. I microblog on twitter, but it does not afford the space to elaborate on a topic.

The main theme of this blog is implementing parallel computers in FPGAs, but I will also use this space to sound off on other matters of interest to me.

For starters I am going to bring forward the archived FPGA CPU News content, bit by bit. Unfortunately the old site was just a big sed script so there is no good automated solution. I will fix linkrot where I can. Otherwise dead links will get dead-url’d and struck out. These articles should follow in reverse chronological order.

For the time being, the old archived site is at and this site will be at When I finish importing the archived content, I will remove the old site (both will point here).

Thank you for visiting.