Monthly Archives: December 2002

Saturday, December 28, 2002

FPGA-FAQ has a nice fresh list of FPGA boards.

Peter Clarke, Semiconductor Business News: Former UK defense unit offers floating-point unit for FPGAs. For MicroBlaze and the Virtex-II Pro’s PowerPC(s). QinetiQ [Quixilica].

‘We’re already seeing applications in image and signal processing systems, control, and support of legacy hardware, where the combination of an FPGA with an embedded microprocessor core and the FPU can provide the functionality and performance of an entire DSP subsystem, said Bill Smith, manager of QinetiQ’s real-time systems laboratory, in statement.’

I’ve been to Malvern several times, lovely place.

Wednesday, December 18, 2002

Free Xilinx PicoBlaze Microcontroller Expands Support to Virtex-II Series FPGAs and CoolRunner-II CPLDs. PicoBlaze User Resources.

Earlier coverage.

Regarding PicoBlaze for CPLDs, e.g. CoolRunner-II, lacking any on-chip block RAM instruction memory, the PB for CR2 requires you provide an external 16-bit wide instruction RAM.  This may prove prove prohibitive in board area and cost.  You can reduce the requirement to 8-bit external memory using a few more macrocells, of course, but in my opinion this application is a better fit for a device with embedded block memory (e.g. Spartan-IIE, etc.).

This does illustrate the utility and value of a modest amount of embedded RAM and/or FLASH in these larger CPLDs — an idea whose time has come.

Monday, December 16, 2002

Xilinx: 90nm Process Technology Drives Down Costs.

IBM: IBM and Xilinx prepare for production of first 90nm chips on 300mm wafers.

UMC: UMC AND XILINX ON TRACK TO MANUFACTURE 90NM PROGRAMMABLE CHIPS ON 300MM WAFERS IN 2003.

Anthony Cataldo, EE Times: IBM, Xilinx tape out first 90-nm FPGAs.

Therese Poletti, San Jose Mercury News: IBM-Xilinx new chip moves to production.

John Blau, IDG News Service: IBM, UMC ready first 90-nanometer chips.

1.2V!

Tuesday, December 3, 2002

Xilinx:Tarari adopts Xilinx Technology for Reconfigurable Content Processor Solutions.

“Tarari content processors are hardware and software-based subsystem building blocks (silicon, boards, etc.) that snap into servers, appliances and network devices, allowing for the first time the inspection of application layer content at network speeds…”

Tarari.

Here, March: Applications of racks full of FPGA multiprocessors:

“I suppose my pet hand-wavy application for these concept chip-MPs is lexing and parsing XML and filtering that (and/or parse table construction for same). Let me set the stage for you. “”Imagine a future in which “web services” are ubiquitous — the internet has evolved into a true distributed operating system, a cloud offering services to several billion connected devices. Imagine that the current leading transport candidate for internet RPC, namely SOAP — (Simple Object Access Protocol, e.g. XML encoded RPC arguments and return values, on an HTTP transport, with interfaces described in WSDL (itself based upon XML Schema)) — imagine SOAP indeed becomes the standard internet RPC. That’s a ton of XML flying around. You will want your routers and firewalls, etc. of the future to filter, classify, route, etc. that XML at wire speed. That’s a ton of ASCII lexing, parsing, and filtering. It’s trivially parallelizable — every second a thousand or a million separate HTTP sessions flash past your ports — and therefore potentially a nice application for rack full of FPGAs, most FPGAs implementing a 100-way parsing and classification multiprocessor.”